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this is information on a product in full production. july 2015 docid023009 rev 6 1/15 STL8DN10LF3 automotive-grade dual n-channel 100 v, 25 m ? typ., 7.8 a stripfet? f3 power mosfet in a powerflat? 5x6 double island package datasheet ? production data figure 1. internal schematic diagram features ? designed for automotive applications and aec-q101 qualified ? logic level v gs(th) ? 175 c maximum junction temperature ? 100% avalanche rated ? wettable flank package applications ? switching applications description this device is a dual n-channel power mosfet developed using stripfet? f3 technology. it is designed to minimize on-resistance and gate charge to provide superior switching performance. 3rzhu)/$7?[grxeohlvodqg order code v ds r ds(on) max i d STL8DN10LF3 100 v 35 m 7.8 a table 1. device summary order code marking packages packing STL8DN10LF3 8dn10lf3 powerflat? 5x6 double island tape and reel www.st.com
contents STL8DN10LF3 2/15 docid023009 rev 6 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
docid023009 rev 6 3/15 STL8DN10LF3 electrical ratings 15 1 electrical ratings table 2. absolute maximum ratings symbol parameter value unit v ds drain-source voltage 100 v v gs gate-source voltage 20 v i d (1),(2) 1. specified by design. not subject to production test. 2. current is limited by bonding, with an r thjc = 2.1 c/w the chip is able to carry 32 a at 25 c. drain current (continuous) at t c = 25 c 20 a i d drain current (continuous) at t c = 100 c 20 a i d (4) drain current (continuous) at t pcb = 25 c 7.8 a i d (4) drain current (continuous) at t pcb =100 c 5.5 a i dm (3),(4) 3. pulse width limited by safe operating area. 4. when mounted on fr-4 board of 1inch2, 2oz cu, t < 10 sec drain current (pulsed) 31.2 a p tot total dissipation at t c = 25c 70 w p tot (4) total dissipation at t pcb = 25c 4.3 w i av not-repetitive avalanche current 7.8 a e as (5) 5. starting t j = 25 c, i d = 7.8 a, v dd = 25 v single pulse avalanche energy 190 mj t j operating junction temperature -55 to 175 c t stg storage temperature c table 3. thermal resistance symbol parameter value unit r thj-case thermal resistance junction-case 2.1 c/w r thj-pcb (1) 1. when mounted on fr-4 board of 1inch2, 2oz cu, t < 10 sec thermal resistance junction-pcb 35 c/w
electrical characteristics STL8DN10LF3 4/15 docid023009 rev 6 2 electrical characteristics (t case = 25 c unless otherwise specified) table 4. on/off states symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage (v gs = 0) i d = 250 a 100 v i dss zero gate voltage drain current (v gs = 0) v ds = 100 v 1 a i gss gate body leakage current (v ds = 0) v gs = 20 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 1 2.5 v r ds(on) static drain-source on- resistance v gs = 10 v, i d = 4 a 25 35 m v gs = 5 v, i d = 4 a 40 50 m table 5. dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds =25 v, f=1 mhz, v gs =0 -970 - pf c oss output capacitance - 115 - pf c rss reverse transfer capacitance - 11.5 - pf q g total gate charge v dd =50 v, i d = 7.8 a v gs =10 v figure 13 - 20.5 - nc q gs gate-source charge - 4 - nc q gd gate-drain charge - 5 - nc r g intrinsic gate resistance f=1 mhz open drain - 3.65 - table 6. switching times symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time v dd =50 v, i d = 7.8 a, r g =4.7 , v gs =10 v figure 14 -8.7-ns t r rise time - 9.6 - ns t d(off) turn-off delay time - 50.6 - ns t f fall time - 5.2 - ns
docid023009 rev 6 5/15 STL8DN10LF3 electrical characteristics 15 table 7. source drain diode symbol parameter test conditions min typ. max unit i sd source-drain current - 7.8 a i sdm (1) 1. pulse width limited by safe operating area source-drain current (pulsed) - 31.2 a v sd (2) 2. pulsed: pulse duration= 300 s, duty cycle 1.5% forward on voltage i sd = 7.8 a, v gs =0 - 1.3 v t rr reverse recovery time i sd = 7.8 a, di/dt = 100 a/s, v dd =48 v, tj=150 c -42.5 ns q rr reverse recovery charge - 87 nc i rrm reverse recovery current - 4.08 a
electrical characteristics STL8DN10LF3 6/15 docid023009 rev 6 2.1 electrical characteristics (curves) figure 2. safe operating area figure 3. thermal impedance i d 10 1 0.1 0.1 1 v ds (v) 10 (a) operation in this area is limited by max r ds(on) 10ms 100ms 1s tj=175c tpcb=25c single pulse am13017v1 10 -4 10 -3 10 -2 10 -1 t p (s) 10 -2 10 -1 k 0.2 0.05 0.02 0.01 0.1 single pulse =0.5 10 0 10 1 10 -3 pcb zth_am13007v1 figure 4. output characteristics figure 5. transfer characteristics i d 15 10 5 0 0 2 v ds (v) 4 (a) 1 3 20 25 5v 4v v gs =10v am13018v1 i d 15 10 5 0 0 2 v gs (v) 4 (a) 1 3 20 25 v ds =4v am13019v1 figure 6. normalized v (br)dss vs temperature figure 7. static drain-source on-resistance v (br)dss -75 t j (c) (norm) -25 75 25 125 0.90 0.94 0.98 1.02 1.06 i d =1ma 1.10 am13010v1 r ds(on) 25.0 24.8 24.6 24.4 2 4 i d (a) (m ) 3 5 25.2 25.4 6 7 v gs =10v am13020v1
docid023009 rev 6 7/15 STL8DN10LF3 electrical characteristics 15 figure 8. gate charge vs gate-source voltage figure 9. capacitance variations v gs 6 4 2 0 0 5 q g (nc) (v) 20 8 10 15 10 v dd =50v i d =7.8a am13021v1 c 1000 100 10 0 40 v ds (v) (pf) 20 60 ciss coss crss 80 am13022v1 figure 10. normalized gate threshold voltage vs temperature figure 11. normalized on-resistance vs temperature v gs(th) 1.0 0.8 0.6 0.4 -75 t j (c) (norm) -25 1.2 75 25 125 i d =250a am13014v1 r ds(on) 1.2 0.8 0.4 0 -75 t j (c) (norm) -25 75 25 125 1.6 2.0 i d =4a v gs =10v am13015v1
test circuits STL8DN10LF3 8/15 docid023009 rev 6 3 test circuits figure 12. switching times test circuit for resistive load figure 13. gate charge test circuit am01468v1 v gs p w v d r g r l d.u.t. 2200 f 3.3 f v dd am01469v1 v dd 47k 1k 47k 2.7k 1k 12v v i =20v=v gmax 2200 f p w i g =const 100 100nf d.u.t. v g figure 14. test circuit for inductive load switching and diode recovery times figure 15. unclamped inductive load test circuit am01470v1 a d d.u.t. s b g 25 a a b b r g g fast diode d s l=100 h f 3.3 1000 f v dd am01471v1 v i p w v d i d d.u.t. l 2200 f 3.3 f v dd figure 16. unclamped inductive waveform figure 17. switching time waveform am01472v1 v (br)dss v dd v dd v d i dm i d am01473v1 v ds t on td on td off t off t f t r 90% 10% 10% 0 0 90% 90% 10% v gs
docid023009 rev 6 9/15 STL8DN10LF3 package information 15 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 18. powerflat? 5x6 double island wf type r package outline %rwwrpylhz 3lq lghqwlilfdwlrq 6lghylhz 7rsylhz 3lq lghqwlilfdwlrq bubw\sh5:)
package information STL8DN10LF3 10/15 docid023009 rev 6 table 8. powerflat? 5x6 double island wf type r mechanical data dim. mm min. typ. max. a 0.80 1.00 a1 0.02 0.05 a2 0.25 b 0.30 0.50 d 5.00 5.20 5.40 d2 4.11 4.31 e 6.20 6.40 6.60 e2 3.50 3.70 e4 0.55 0.75 e5 0.08 0.28 e6 2.35 2.55 e7 0.40 0.60 e1.27 l 0.70 0.90 l1 0.275 k 1.275 1.575
docid023009 rev 6 11/15 STL8DN10LF3 package information 15 figure 19. powerflat? 5x6 double island recommended footprint (dimensions are in mm) bubw\sh5:)bis
packing information STL8DN10LF3 12/15 docid023009 rev 6 5 packing information figure 20. powerflat 5x6 wf tape (a) figure 21. powerflat? 5x6 package orientation in carrier tape 1.50 0.0 + 0.1 do 4.0 0.1(ii) po 1.75 0.1 e1 1.50 min d1 2.0 0.05(i) p2 y y r0.30 max 0.30 0.05 t section y-y measured from centreline of sprocket hole to centreline of pocket. cumulative tolerance of 10 sprocket holes is 0.20 . measured from centreline of sprocket hole to centreline of pocket. (i) (ii) (iii) base and bulk quantity 3000 pcs p1(8.000.1) ao(6.700.1) f(5.500.0.05)(iii) w(12.000.1) bo (5.350.05) ko (1.200.1) 8234350_tapewf_rev_c pin 1 identification
docid023009 rev 6 13/15 STL8DN10LF3 packing information 15 figure 22. powerflat? 5x6 reel 2.20 ?21.2 13.00 core detail 2.50 1.90 r0.60 77 128 ?a r1.10 2.50 4.00 r25.00 part no. w1 w2 18.4 (max) w3 06 ps esd logo at t e n t i o n observe precautions for handling electrostatic sensitive devices 11.9/15.4 12.4 (+2/-0) a 330 (+0/-4.0) all dimensions are in millimeters ?n 178(2.0) 8234350_reel_rev_c
revision history STL8DN10LF3 14/15 docid023009 rev 6 6 revision history table 9. document revision history date revision changes 28-mar-2012 1 first release. 20-jun-2012 2 added section 2.1: electrical characteristics (curves) . updated section 4: package information and title on the cover page. 26-jun-2012 3 updated figure 9: capacitance variations . document status promoted from preliminary to production data. 28-oct-2013 4 ? updated: section 4: package information and section 5: packing information ? updated title and features in cover page ? modified: v gs(th) value in table 4 ? minor text changes 20-feb-2014 5 ? added: features in cover page ? added: note 1 in table 1 ? added: table 19 and table 9 ? added: figure 20 ? minor text changes 10-jul-2015 6 ? updated title and description in cover page. ? updated section 4: package information .
docid023009 rev 6 15/15 STL8DN10LF3 15 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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